The present invention relates in general to fast logic circuits, and more particularly to a family of new GaAs MESFET Source Coupled logic circuits including push pull output buffers which exhibits astonishing output driving capability and very low power consumption at fast switching speeds.
The new circuits are derived from the high speed Source Coupled FET Logic circuits (SCFL) also alternatively called Current Mode Logic circuits (CML) in the technical literature.
Examples of conventional CML/SCFL circuits are given in the following references:
Ref 1: A Source Coupled FET Logic--A New Current-Mode Approach to GaAs Logics, by Shin'Ichi Katsu et al., IEEE transactions on electron devices, Vol. ED-32, No. 6, June 1985.
Ref. 2: A CML GaAs 4Kb SRAM, by Kazukio Takahashi et al., 1985 IEEE International Solid-State Circuits Conference, Digest of technical papers, pp 68-69, (see more particularly FIG. 2).
Ref. 3: Low dissipation current GaAs prescaler IC, by K. Hasegawa et al., Electronics Letters 27th Feb. 1986 Vol. 22, No 5, pp 251-252 (see more particularly FIG. 2).
The conventional SCFL circuits are derived from the well known Emitter Coupled Logic circuits (ECL) except that the bipolar transistors are replaced with FET devices, and operate in a similar way. They are generally used in high speed applications where the output buffer circuits require large output currents. An interesting feature offered by SCFL circuits is their compatibility with ECL circuits, which allows an SCFL circuit to be directly connected to circuits manufactured using ECL technology.
FIG. 1 shows a typical dual phase SCFL circuit implementation as it may be constructed from the above cited prior art. The circuit or gate referenced 10 basically consists of a differential amplifier DA and of two source follower output buffers OB11 and OB12. The differential amplifier forms a tree comprised of two branches coupled intermediate a current source at node 11 and a first supply voltage VH at node 12. The current source is formed by FET T10, with its gate and source shorted to function as a linear load over the operating range of circuit 10, coupled to a second supply voltage VD. The first branch comprises FET T11, the gate electrode of which is connected to a reference voltage VREF, connected in series with resistor R2. The other branch comprises FET T12 connected in series with resistor R1. A logic input signal E1 is applied on the input terminal I1 of FET T12. The other end of resistors R1 and R2 is coupled to said first supply voltage VH at node 12. Circuit 10 pertains to the SCFL technology because the source regions of FETs T11 and T12 are coupled together at node 11. FETs T11 and T12 operate as current switches. First and second output signals S1 and S2 of the differential amplifier are available at nodes 13 and 14 respectively intermediate said resistors and said current switches. Said nodes 13 and 14 are respectively connected to the inputs of two source follower output buffers OB11 and OB12 mounted in parallel between third and fourth supply voltages. Usually, as represented in FIG. 1, said third supply voltage is identical to said first supply voltage and said fourth supply voltage is identical to said second supply voltage. The first source follower output buffer OB1 comprises active FET T13 loaded by resistively mounted FET T14. Generally speaking, shorted source-gate FETs are preferable to resistors. Similarly, the second source follower output buffer OB2 comprises FETs T15 and T16. Inputs of said source follower output buffers are the gate electrodes of active FETs T13 and T15. The combination of the two source-follower output buffers forms output circuit block 16.
When a logic input signal E1 is applied to the gate electrode of FET T12 in the differential amplifier, the voltage E1 is compared to the fixed reference voltage VREF applied to the gate electrode of T11, so that either FET T11 or T12 (but never both) can turn on in a current mode, depending on whether voltage E1 is higher or lower than VREF.
As explained above, the differential amplifier DA provides first and second output signals S1 and S2 respectively at node 13 and at node 14. Therefore, the gate electrode of FET T13 is driven by S1 which is the OUT OF PHASE signal, while the gate electrode of FET T15 is driven by S2 which is the IN PHASE signal. It is remarkable to notice that, both signals S1 and S2 are complementary (S1=S2) and there is no skew between them. In others words, signals S1 and S2 are in perfect synchronism and simultaneity. First and second output buffer stages operate without inverting the signals, so that first and second circuit output signals A and B of circuit 10 are available in a complementary form at first and second circuit output terminals 17 and 18. These terminals are respectively at the same potential as the common nodes between FETs T13 and T14 on the one hand, and FETs T15 and T16 on the other hand. The logic function F which is performed by circuit 10 is INVERT, so that in terms of logic signals, A=S1=E1 and B=S2=E1.
As long as a single FET T12 is used, circuit 10 operates as an inverter on one circuit output terminal. However, because logic functions F more complex than INVERT are usually required, additional transistors have to be connected to FET T12, in parallel and/or in series. For example, adding two FETs, T17 and T18 mounted in parallel with FET T12 and respectively driven by logic input signals E2 and E3, forms a logic block referenced 19 which implements a 3 Way OR/NOR function in circuit 10.
The circuit of FIG. 1 has been shown implemented with FETs of the N type with both enhancement (E) and depletion (D) devices.
Although SCFL circuits may be designed in various fashions, combining (1) a differential amplifier structure supplying two complementary and simultaneous output logic signals (referred to as S1 and S2), and (2) a pair of source follower output buffer stages respectively driven by said output logic signals, is a common practice to all versions of SCFL circuits of the prior art (see FIG. 2 of Refs. 2 and 3, for instance).
It is also important to notice that each source follower output buffer may be understood as being comprised of an active pull up device (e.g. T13) and a passive pull down device (e.g. T14) connected in series. The latter device acts as a passive load. The active pull up devices T13 and T15 are loaded with important line capacitances (including wiring and fan-out capacitances) represented by C1 and C2 at circuit output terminals 17 and 18 respectively. Both capacitances C1 and C2 are connected to a reference potential, which in the present case is the ground potential or GND.
The usual values for capacitances C1 and C2 which are used for simulating circuit 10 are selected in the range extending from 0.1 to 4 pF.
Finally, adjusting transistor sizes and resistor values is important to fix operating voltage levels and swings. In particular, the size of FET T10 and values of resistors R1 and R2 are determining parameters in that respect. For a given standard GaAs MESFET technology, typical parameters are given below in TABLE I:
TABLE I ______________________________________ Components Parameter Values Units ______________________________________ T10 FET size 14.1 .mu.m T11 " 34.2 " T13, T15 " 34.2 " T12, T17, T18 " 17.1 " T14, T16 " 14.1 " R1, R2 Resistance 1.7 K-ohms VD Voltage -0.7 V VH " 1.4 " VREF " 0.26 " C1, C1 Capacitance 0.1 to 4 pF E1, E2, E3 Voltage swing 50 to 650 mV ______________________________________
Under these conditions, the circuit of FIG. 1 is perfectly compatible with ECL logic levels, the supply voltages, levels of both input and circuit output signals being identical.
SCFL logic technology is widely used, because it provides very fast switching. It is also nearly independent of the threshold voltages of the FETs since the critical level of the transfer characteristics is equal to the externally applied reference voltage VREF. SCFL circuits are particularly attractive when metal-semiconductor FETs (MESFETs) are employed with a GaAs substrate.
When built with high enough transconductance devices, such as short channel GaAs MESFETs, SCFL circuits can provide better speed capabilities than their bipolar counterparts but they suffer from the same disadvantage of high power consumption.
The circuit of FIG. 1 dissipates big power because each source follower output buffer (e.g. OB11) essentially consists of an active pull up device loaded by a passive pull down device typically a FET (e.g. T14) operating as an equivalent resistor R. This FET has to be a big device to have a small resistance, so that in AC conditions, capacitance, e.g. C1, can discharge fast at down going transition of the signal. For similar reasons, the active pull up device, e.g. T13, is also a big device so that capacitance C1 is rapidly charged during up going transitions. Unfortunately, in the quiescent state when FET T13 is on, this low value resistance R creates a large DC sink current between VH and VD (which is negative) because FET T14 is of the depletion type. This current is not necessary. It is also to be noted that the use of the negative supply voltage VD, also causes to a slowing in the discharge capacitance C1 in AC conditions.
Most of this power consumption comes from this output sink current necessary to discharge the output capacitive loads C1 and C2 to VD.
Moreover, because the sink current is defined by a passive load (e.g. T14), the output down level exhibits a poor definition.
Finally, the circuit of FIG. 1 also suffers from its asymmetrical operation. Down going transitions measured by the fall time (Tfall) of devices are slower than up going transitions measured by the rise time (Trise). This difference comes from the sink current which is usually smaller than the transient current provided by the pull up device (e.g. T13) since its DC value is limited by the power dissipation.
To summarize, the severe drawbacks due to the usage at the circuit output of the standard source-follower buffers of the prior art are listed below:
(a) The large DC sink current necessary to pull down the capacitive loads C1 and C2 causes a large power dissipation.
(b) The DC sink current slows down the upgoing transition because it is subtracted from the current supplied by the source-follower output buffer and therefore decreases the current that charges up the loading capacitances C1 and C2.
(c) In most cases the DC sink current has to be limited to a reasonable value which is still not large enough to insure a fast turn off time when the pull up device is switched off. As a result, the down going transition is generally two to three times slower than the up going transition, thereby causing an unbalanced response of the circuit.
However, this type of circuit is still greatly desired for high speed applications not only because of its fast switching times but also because of its large tolerance to device threshold variations.
Since power dissipation is a limiting factor of paramount importance in high speed applications, circuits that have reduced power consumption are crucial to the development of advanced Ultra High Speed Integrated Circuits (UHSICs). In addition, it is also highly desirable to have circuits with symmetrical operations, say with well balanced up and down going transitions. Accordingly, there is a real need for improved output buffers obviating all these inconveniences.